5.23. Double Shift Cyclic, Count in Register


Addr
Mode  Mnemonic          Format/Opcode
                           8      4      4
                        ----------------------
R     DSCR   RA,RB      |  6F  |  RA  |  RB  |    |(RB)| <= 32
                        ----------------------   

Description. The concatenated contents of registers RA and RA+1 are shifted cyclically N positions, where register RB contains the count, N. If the count is positive ((RB0)=0), the shift direction is left.

If the count is negative (2's complement notation, (RB0)=1), the shift direction is right. The condition status, CS, is set based on the result in RA and RA+1.

Note: N = 0 represents a shift of zero positions.

Note: If |N| >= 32, the fixed point overflow occurs, no shifting occurs, and this instruction is treated as a NOP (see Section 5.96).

Note: (See "Description" of the double shift cyclic instruction, DSLC (see Section 5.17), for the definition of shift operations.)

Note: The contents of RB remain unchanged, unless RA = RB; in this event, the contents are shifted N positions.

Register Transfer Description.

PI4 <-- 1, exit, if |N| >= 32;
(RA,RA+1) <-- (RA,RA+1) Shifted left cyclically by (RB) positions
        if 32 >= (RB) >== 0;
(RA,RA+1) <-- (RA,RA+1) Shifted right cyclically by -(RB) positions
        if 0 >= (RB) >== -32;
(CS) <-- 0010  if (RA,RA+1) = 0;
(CS) <-- 0001  if (RA,RA+1) < 0;
(CS) <-- 0100  if (RA,RA+1) >= 0;

Registers Affected. RA, RA+1, RB, CS, PI