| MIL-STD-1750A: Military Standard Sixteen-Bit Computer Instruction Set Architecture | ||
|---|---|---|
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Addr
Mode Mnemonic Format/Opcode
8 4 4
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R DSAR RA,RB | 6E | RA | RB | |(RB)| <= 32
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Description. The concatenated contents of register RA and RA+1 are shifted arithmetically N positions where register RB contains the count, N. If the count is positive ((RB0)=0), then the shift direction is left. If the count is negative (2's complement notation, (RB0)=1), then the shift direction is right. The condition status, CS, is set based on the result in RA and RA+1.
Note: N = 0 represents a shift of zero positions.
Note: If |N| >= 32, the fixed point overflow occurs, no shifting occurs, and this instruction is treated as a NOP (see Section 5.96).
Note: The contents of RB remain unchanged, unless RA = RB; in this event, the contents are shifted N positions.
Note: (See "Description" of the double shift arithmetic instruction, DSRA (see Section 5.16), for the definition of the right shift operation. Left shift causes "zeros" to be shifted into low order position of result.)
Note: Fixed point overflow occurs if the sign bit is changed during a left shift.
Register Transfer Description.
PI4 <-- 1, exit, if |N| >= 32;
(RA,RA+1) <-- (RA,RA+1) Shifted left arithmetically (RB) positions,
if 32 >= (RB) >== 0;
(RA,RA+1) <-- (RA,RA+1) Shifted right arithmetically -(RB) positions,
if 0 >= (RB) >== -32;
PI4 <-- 1, if (RA0) changes during the shift;
(CS) <-- 0010 if (RA,RA+1) = 0;
(CS) <-- 0001 if (RA,RA+1) < 0;
(CS) <-- 0100 if (RA,RA+1) >= 0;
Registers Affected. RA, RA+1, RB, CS, PI