| MIL-STD-1750A: Military Standard Sixteen-Bit Computer Instruction Set Architecture | ||
|---|---|---|
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Addr
Mode Mnemonic Format/Opcode
8 4 4 16
D JC C,LABEL --------------------------------------
DX JC C,LABEL,RX | 70 | C | RX | | LABEL |
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8 4 4 16
I JCI C,ADDR --------------------------------------
IX JCI C,ADDR,RX | 71 | C | RX | | ADDR |
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Description. This is a conditional jump instruction wherein the instruction sequence jumps to the Derived Address, DA, if a logical one results from the following operation:
The 4-bit C field is bit-by-bit ANDed with the 4-bit condition status, CS
The resulting 4-bits are ORed together
or if C = 7 or C = F.
Otherwise, the next sequential instruction is executed.
Condition Codes.
C2 C16 Jump Condition Mnemonic 0000 0 NOP -- -- -- 0001 1 less than (zero) LT LZ M 0010 2 equal to (zero) EQ EZ -- 0011 3 less than or equal to (zero) LE LEZ NP 0100 4 greater than (zero) GT GZ P 0101 5 not equal to (zero) NE NZ -- 0110 6 greater than or equal to (zero) GE GEZ NM 0111 7 unconditional -- -- -- 1000 8 carry CY -- -- 1001 9 carry or LT -- -- -- 1010 A carry or EQ -- -- -- 1011 B carry or LE -- -- -- 1100 C carry or GT -- -- -- 1101 D carry or NE -- -- -- 1110 E carry or GE -- -- -- 1111 F unconditional -- -- --
Register Transfer Description.
(IC) <-- DA if C = 7, or
if C = F, or
if (C
0 ^ CS0) v (C1 ^ CS
1) v (C2 ^ CS2) v (C3 ^ CS
3) = 1;
Registers Affected. IC (if jump is executed)