| MIL-STD-1750A: Military Standard Sixteen-Bit Computer Instruction Set Architecture | ||
|---|---|---|
| Prev | Chapter 5. Detailed Requirements | Next |
Addr
Mode Mnemonic Format/Opcode
8 4 4
-----------------------
R DSRA RB,N | 67 | N-1 | RB | 1 <= N <= 16
-----------------------
Description. The concatenated contents of the Derived Address, DA, and DA+1 (i.e., the concatenated contents of RB and RB+1), are shifted right arithmetically N positions. The shifted results are stored in RB and RB+1. The double right shift arithmetic operation is as follows: the sign bit of RB, which is not changed, is copied into the next position for each position shifted, bits shifted out of the least significant position of RB enter the sign bit position of RB+1, and bits shifted out of the least significant bit position of RB+1 are lost. The condition status, CS, is set based on the result in register RB and RB+1.
Note: N-1 = 0 represents a shift of one position.
Note: N-1 = 15 represents a shift of sixteen positions.
RB, RB+1 Before Shift
0 RB 15 0 RB+1 15
----------------------------- -----------------------------
| sabc | defg | hijk | lmnp | | sqrs | tuvw | xyzz | zzzz |
| 1 | | | | | 2 | | | |
----------------------------- -----------------------------
RB, RB+1 After Shift (N=4)
0 RB 15 0 RB+1 15
----------------------------- -----------------------------
| ssss | sabc | defg | hijk | | lmnp | sqrs | tuvw | xyzz |
| 1111 | 1 | | | | | 2 | | |
----------------------------- -----------------------------
Register Transfer Description.
(RB,RB+1) <-- (RB,RB+1) Shifted right arithmetically by N positions;
(CS) <-- 0010 if (RB,RB+1) = 0;
(CS) <-- 0001 if (RB,RB+1) < 0;
(CS) <-- 0100 if (RB,RB+1) >= 0;
Registers Affected. RB, RB+1, CS