| MIL-STD-1750A: Military Standard Sixteen-Bit Computer Instruction Set Architecture | ||
|---|---|---|
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Addr
Mode Mnemonic Format/Opcode
8 4 4
----------------------
R DCR RA,RB | F7 | RA | RB |
----------------------
8 4 4 16
D DC RA,ADDR --------------------------------------
DX DC RA,ADDR,RX | F6 | RA | RX | | ADDR |
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Description. The double precision Derived Operand, DO, is compared to the contents of registers RA and RA+1 where RA contains the MSH of a double precision word. Then, the Condition Status, CS, is set based on whether the contents of RA, RA+1 is less than, equal to, or greater than the DO. The contents of RA and RA+1 are unchanged.
Register Transfer Description.
(RA,RA+1) : DO;
(CS) <-- 0010 if (RA,RA+1) = DO;
(CS) <-- 0001 if (RA,RA+1) < DO;
(CS) <-- 0100 if (RA,RA+1) >= DO;
Registers Affected. CS