| MIL-STD-1750A: Military Standard Sixteen-Bit Computer Instruction Set Architecture | ||
|---|---|---|
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Addr
Mode Mnemonic Format/Opcode
8 4 4
----------------------
R FCR RA,RB | F9 | RA | RB |
----------------------
4 2 2 8 12<=BR<=15
----------------------
B FCB BR,DSPL | 3 | 3 | BR' | DSPL | BR'=BR-12
---------------------- RA=R0
4 2 2 4 4 12<=BR<=15
------------------------
BX FCBX BR,RX | 4 | 0 | BR' | D | RX | BR'=BR-12
------------------------ RA=R0
4 8 8 16
D FC RA,ADDR --------------------------------------
DX FC RA,ADDR,RX | F8 | RA | RX | | ADDR |
--------------------------------------
Description. The floating point number in registers RA and RA+1 is compared to the floating point Derived Operand, DO. Then, the Condition Status, CS, is set based on whether the contents of RA, RA+1 is less than, equal to, or greater than the DO. The contents of RA and RA+1 are unchanged.
Note: This instruction does not cause an overflow to occur.
Register Transfer Description.
(RA, RA+1) : DO;
(CS) <-- 0010 if (RA,RA+1) = DO;
(CS) <-- 0001 if (RA,RA+1) < DO;
(CS) <-- 0100 if (RA,RA+1) >= DO;
Registers Affected. CS