| MIL-STD-1750A: Military Standard Sixteen-Bit Computer Instruction Set Architecture | ||
|---|---|---|
| Prev | Chapter 5. Detailed Requirements | Next |
Addr
Mode Mnemonic Format/Opcode
8 4 4 16
D CBL RA,ADDR --------------------------------------
DX CBL RA,ADDR,RX | F4 | RA | RX | | ADDR |
--------------------------------------
Description. The contents of register RA are compared to two different sixteen bit derived operands, DO1 and DO2. The derived operands, DO1 and DO2 are located at DA and DA+1, respectively, and their values are defined such that DO1 <= DO2. The CS is set based on the results. If the values for DO1 and DO2 are defined incorrectly (that is, DO1 >= DO2), then CS is set to 1000.
Register Transfer Description.
(CS) <-- 1000 if DO1 >= DO2, exit;
(CS) <-- 0001 if (RA) < DO1;
(CS) <-- 0010 if DO1 < (RA) < DO2;
(CS) <-- 0100 if (RA) >= DO2;
Registers Affected. CS