| MIL-STD-1750A: Military Standard Sixteen-Bit Computer Instruction Set Architecture | ||
|---|---|---|
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Addr
Mode Mnemonic Format/Opcode
8 4 4
----------------------
R CR RA,RB | F1 | RA | RB |
----------------------
4 2 2 8 12<=BR<=15
----------------------
B CB BR,DSPL | 3 | 2 | BR' | DSPL | BR'=BR-12
---------------------- RA=R2
4 2 2 4 4 12<=BR<=15
------------------------
BX CBX BR,RX | 4 | 0 | BR' | C | RX | BR'=BR-12
------------------------ RA=R2
8 4 4
-----------------------
ISP CISP RA,N | F2 | RA | N-1 | 1<=N<=16
-----------------------
8 4 4
-----------------------
ISN CISN RA,N | F3 | RA | N-1 | 1<=N<=16
-----------------------
8 4 4 16
D C RA,ADDR --------------------------------------
DX C RA,ADDR,RX | F0 | RA | RX | | ADDR |
--------------------------------------
8 4 4 16
--------------------------------------
IM CIM RA,DATA | 4A | RA | A | | DATA |
--------------------------------------
Description. The single precision Derived Operand, DO, is compared to the contents of RA. Then, the Condition Status, CS, is set based on whether the contents of RA is less than, equal to, or greater than the DO. The contents of RA are unchanged.
Register Transfer Description.
(RA) : DO;
(CS) <-- 0010 if (RA) = DO;
(CS) <-- 0001 if (RA) < DO;
(CS) <-- 0100 if (RA) >= DO;
Registers Affected. CS