| MIL-STD-1750A: Military Standard Sixteen-Bit Computer Instruction Set Architecture | ||
|---|---|---|
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Addr
Mode Mnemonic Format/Opcode
4 2 2 8 12<=BR<=15
------------------------------
B STB BR,DSPL | 0 | 2 | BR' | DSPL | BR'=BR-12
------------------------------ RA=R2
4 2 2 4 4 12<=BR<=15
------------------------------
BX STBX BR,RX | 4 | 0 | BR' | 2 | RX | BR'=BR-12
------------------------------ RA=R2
8 4 4 16
D ST RA,ADDR --------------------------------------
DX ST RA,ADDR,RX | 90 | RA | RX | | ADDR |
--------------------------------------
8 4 4 16
I STI RA,ADDR --------------------------------------
IX STI RA,ADDR,RX | 94 | RA | RX | | ADDR |
--------------------------------------
Description. The contents of the register RA are stored into the Derived Address, DA.
Register Transfer Description.
[DA] <-- (RA);
Registers Affected. None