| MIL-STD-1750A: Military Standard Sixteen-Bit Computer Instruction Set Architecture | ||
|---|---|---|
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Addr
Mode Mnemonic Format/Opcode
8 4 4 16
D STC N,ADDR -------------------------------------
DX STC N,ADDR,RX | 91 | N | RX | | ADDR |
-------------------------------------
8 4 4 16
I STCI N,ADDR -------------------------------------
IX STCI N,ADDR,RX | 92 | N | RX | | ADDR |
-------------------------------------
Description. The constant N, where N is an integer (0 <= N <= 15) is stored at the Derived Address, DA. For the special case of storing zero into memory the mnemonics STZ ADDR,RX for direct addressing and STZI ADDR,RX for indirect addressing may be used. In this special case, the N field equals 0.
Register Transfer Description.
[DA] <-- N, where 0 <= N <= 15;
Registers Affected. None