| MIL-STD-1750A: Military Standard Sixteen-Bit Computer Instruction Set Architecture | ||
|---|---|---|
| Prev | Chapter 5. Detailed Requirements | Next |
Addr
Mode Mnemonic Format/Opcode
8 4 4 16
D LLB RA,ADDR --------------------------------------
DX LLB RA,ADDR,RX | 8C | RA | RX | | ADDR |
--------------------------------------
8 4 4 16
I LLBI RA,ADDR --------------------------------------
IX LLBI RA,ADDR,RX | 8E | RA | RX | | ADDR |
--------------------------------------
Description. The LSH (lower byte) of the Derived Operand, DO, is loaded into the LSH (lower byte) of register RA. The MSH (upper byte) of RA is unaffected. The condition status, CS, is set based on the result in RA.
Register Transfer Description.
(RA)8-15 <-- DO8-15;
(CS) <-- 0010 if (RA) = 0;
(CS) <-- 0001 if (RA) < 0;
(CS) <-- 0100 if (RA) >= 0;
Registers Affected. RA, CS