5.42. Load from Upper Byte


Addr
Mode  Mnemonic          Format/Opcode
                           8      4      4            16
D     LUB   RA,ADDR     --------------------------------------
DX    LUB   RA,ADDR,RX  |  8B  |  RA  |  RX  |  |    ADDR    |
                        --------------------------------------
                           8      4      4            16
I     LUBI  RA,ADDR     --------------------------------------
IX    LUBI  RA,ADDR,RX  |  8D  |  RA  |  RX  |  |    ADDR    |
                        --------------------------------------

Description. The MSH (upper byte) of the Derived Operand, DO, is loaded into the LSH (lower byte) of register RA. The MSH (upper byte) of RA is unaffected. The condition status, CS, is set based on the result in RA.

Register Transfer Description.

(RA)8-15 <-- DO0-7;
(CS) <-- 0010  if (RA) = 0;
(CS) <-- 0001  if (RA) < 0;
(CS) <-- 0100  if (RA) >= 0;

Registers Affected. RA, CS