| MIL-STD-1750A: Military Standard Sixteen-Bit Computer Instruction Set Architecture | ||
|---|---|---|
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Addr
Mode Mnemonic Format/Opcode
8 4 4 16
D EFL RA,ADDR ----------------------------------------
DX EFL RA,ADDR,RX | 8A | RA | RX | | ADDR |
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Description. The extended precision floating point Derived Operand, DO, is loaded into registers RA, RA+1, and RA+2 such that the most significant 16-bits of the word are loaded into register RA. The condition status, CS, is set based on the results in registers RA, RA+1, and RA+2.
Register Transfer Description.
(RA, RA+1, RA+2) <-- DO;
(CS) <-- 0010 if (RA, RA+1, RA+2) = 0;
(CS) <-- 0001 if (RA, RA+1, RA+2) < 0;
(CS) <-- 0100 if (RA, RA+1, RA+2) >= 0;
Registers Affected. RA, RA+1, RA+2, CS