5.77. Single Precision Integer Divide with 32-Bit Dividend


Addr
Mode  Mnemonic          Format/Opcode
                           8      4      4
                        ----------------------
R     DR    RA,RB       |  D5  |  RA  |  RB  |
                        ----------------------
                          4   2   2     8         12<=BR<=15
                        ---------------------- 
B     DB    BR,DSPL     | 1 | 3 | BR' | DSPL |    BR'=BR-12
                        ----------------------    RA=R2
                          4   2   2     4   4     12<=BR<=15
                        ------------------------ 
BX    DBX   BR,RX       | 4 | 0 | BR' | 7 | RX |  BR'=BR-12
                        ------------------------  RA=R2
                           8      4      4           16
D     D     RA,ADDR     --------------------------------------
DX    D     RA,ADDR,RX  |  D4  |  RA  |  RX  |  |    ADDR    |
                        --------------------------------------
                           8      4      4           16
                        --------------------------------------
IM    DIM   RA,DATA     |  4A  |  RA  |  5   |  |    DATA    |
                        --------------------------------------

Description. The contents of registers RA and RA+1, a double precision 2's complement number, are divided by the Derived Operand, DO, a single precision, 2's complement number. RA contains the MSH of the 32-bit dividend. The result is stored in registers RA and RA+1 such that RA stores the single precision integer quotient and RA+1 stores the remainder. The Condition Status, CS, is set based on the result in RA. A fixed point overflow occurs if the divisor equals zero or if a positive quotient exceeds 7FFF16 or a negative quotient is less than 800016.

Note: The sign of the non-zero remainder is the same as that of the dividend.

Register Transfer Description.

(RQ, RQ+1, RR) <-- (RA,RA+1) / DO;
PI4 <-- 1, if DO = 0 or (RQ, RQ+1) > 0000 7FFF 16 or (RQ, RQ+1) < FFFF 8000 16
(RA) <-- (RQ+1)
(RA+1) <-- (RR)
(CS) <-- 0010  if (RA) = 0;
(CS) <-- 0001  if (RA) < 0;
(CS) <-- 0100  if (RA) > 0;



Registers Affected. RA, RA+1, CS, PI