5.76. Single Precision Integer Divide with 16-Bit Dividend


Addr
Mode  Mnemonic          Format/Opcode
                           8      4      4
                        ----------------------
R     DVR   RA,RB       |  D1  |  RA  |  RB  |
                        ----------------------
                           8      4      4
                        ----------------------
ISP   DISP  RA,N        |  D2  |  RA  |  N-1 |    1 <= N <= 16
                        ----------------------
                           8      4      4
                        ----------------------
ISN   DISN  RA,N        |  D3  |  RA  |  N-1 |    1 <= N <= 16
                        ----------------------
                           8      4      4           16
D     DV    RA,ADDR     --------------------------------------
DX    DV    RA,ADDR,RX  |  DO  |  RA  |  RX  |  |    ADDR    |
                        --------------------------------------
                           8      4      4           16
                        --------------------------------------
IM    DVIM  RA,DATA     |  4A  |  RA  |  6   |  |    DATA    |
                        --------------------------------------

Description. The contents of register RA are divided by the Derived Operand, DO, a single precision, 2's complement number. The result is stored in registers RA and RA+1 such that RA stores the single precision integer quotient and RA+1 stores the remainder. The Condition Status, CS, is set based on the result in RA. A fixed point overflow occurs if the divisor, DO, is zero, or if the dividend is 800016 and the divisor is FFFF16.

Note: The sign of the non-zero remainder is the same as the sign of the dividend.

Register Transfer Description.

(RA,RA+1) <-- (RA) / DO;
PI4 <-- 1, if DO = 0 or {RA = 8000 16 and DO = FFFF16};
(CS) <-- 0010  if (RA) = 0;
(CS) <-- 0001  if (RA) < 0;
(CS) <-- 0100  if (RA) > 0;



Registers Affected. RA, RA+1, CS, PI