| MIL-STD-1750A: Military Standard Sixteen-Bit Computer Instruction Set Architecture | ||
|---|---|---|
| Prev | Chapter 5. Detailed Requirements | Next |
Addr
Mode Mnemonic Format/Opcode
8 4 4
--------------------
S BPT | FF | F | F |
--------------------
Description. This instruction is typically used for halting the processor during maintenance and diagnostic procedures when the maintenance console is connected to the system. If the console is not connected, this instruction is treated as a NOP (see Section 5.96). Restarting the processor after a BPT can only be done by: the maintenance console or the power on sequence.
Register Transfer Description.
None
Registers Affected. None