| MIL-STD-1750A: Military Standard Sixteen-Bit Computer Instruction Set Architecture | ||
|---|---|---|
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Addr
Mode Mnemonic Format/Opcode
8 4 4
----------------------
R EFMR RA,RB | CB | RA | RB |
----------------------
8 4 4 16
D EFM RA,ADDR --------------------------------------
DX EFM RA,ADDR,RX | CA | RA | RX | | ADDR |
--------------------------------------
Description. The extended precision floating Derived Operand, DO, is extended floating point multiplied by the contents of registers RA, RA+1, and RA+2. The result is stored in registers RA, RA+1, and RA+2. The process of the operation is as follows: the exponent of the operands are added. If the sum exceeds 7F16, a floating point overflow occurs. If the sum is less than 8016, then underflow occurs and the result set to zero. The operand mantissas are multiplied and the result normalized and stored in RA, RA+1, and RA+2. The condition status, CS, is set based on the result in RA, RA+1, and RA+2.
Register Transfer Description.
n = EA + EO;
PI3 <-- 1, EA <-- 7F
16, MA <-- 7FFF FF FFFF
16, exit, if n >= 7F
16 and MA0 = MO0;
PI3 <-- 1, EA <-- 7F
16, MA <-- 8000 00 0000
16, exit, if n >= 7F
16 and MA0 /= MO
0;
PI6 <-- 1, EA <-- 0, MA <-- 0, exit, if n < 80
16;
MP <-- MA x MO; (integer multiply)
MP <-- MP shift left 1 position;
n <-- n + 1, MP0-39 <-- 4000 00 0000
16, if MP0-39 = 8000 00 0000
16;
PI3 <-- 1, EA <-- 7F
16, MA <-- 7FFF FF FFFF
16, exit, if n >= 7F
16 and MP0 = 0;
PI3 <-- 1, EA <-- 7F
16, MA <-- 8000 00 0000 , exit, if n >= 7F
16 and MP0 = 1;
n, MP <-- normalized n, MP;
PI6 <-- 1, EA <-- 0, MA <-- 0, if n < 80
16;
EA <-- n;
MA <-- MP0-39;
(CS) <-- 0010 if (RA,RA+1,RA+2) = 0;
(CS) <-- 0001 if (RA,RA+1,RA+2) < 0;
(CS) <-- 0100 if (RA,RA+1,RA+2) >= 0;
Registers Affected. RA, RA+1, RA+2, CS, PI