| MIL-STD-1750A: Military Standard Sixteen-Bit Computer Instruction Set Architecture | ||
|---|---|---|
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Addr
Mode Mnemonic Format/Opcode
8 4 4
----------------------
R FMR RA,RB | C9 | RA | RB |
----------------------
4 2 2 8 12<=BR<=15
----------------------
B FMB BR,DSPL | 2 | 2 | BR' | DSPL | BR'=BR-12
---------------------- RA=R0
4 2 2 4 4 12<=BR<=15
------------------------
BX FMBX BR,RX | 4 | 0 | BR' | A | RX | BR'=BR-12
------------------------ RA=R0
8 4 4 16
D FM RA,ADDR --------------------------------------
DX FM RA,ADDR,RX | C8 | RA | RX | | ADDR |
--------------------------------------
Description. The floating point Derived Operand, DO, is floating point multiplied by the contents of register RA and RA+1. The result is stored in register RA and RA+1. The process of the operation is as follows: the exponents of the operands are added. If the sum exceeds 7F16, a floating point overflow occurs. If the sum is less than 8016, then underflow occurs and the result set to zero. The operand mantissas are multiplied and the result normalized and stored in RA and RA+1. An exceptional case is when both operands are negative powers of two: (-1.0 x 2n ) x (-1.0 x 2m); the result is a 0.5 x 2n+m+1. If n+m = 7F16, this shall yield an exponent overflow, floating point overflow occurs. Also, if is possible that the normalization process may yield an exponent underflow; if this occurs, then the result is forced to zero. The condition status, CS, is set based on the result in RA and RA+1.
Register Transfer Description.
n = EA + EO;
PI3 <-- 1, EA <-- 7F
16, MA <-- 7FFF FF16, exit, if n >= 7F
16 and MA0 = MO0;
PI3 <-- 1, EA <-- 7F
16, MA <-- 8000 0016, exit, if n >= 7F
16 and MA0 /= MO
0;
PI6 <-- 1, EA <-- 0, MA <-- 0, exit, if n < 80
16;
MP <-- MA x MO; (integer multiply)
MP <-- MP shift left 1 position;
n <-- n + 1, MP0-23 <-- 4000 00
16, if MP0-23 = 8000 00
16;
PI3 <-- 1, EA <-- 7F
16, MA <-- 7FFF FF16, exit, if n >= 7F
16 and MP0 = 0;
PI3 <-- 1, EA <-- 7F
16, MA <-- 8000 0016, exit, if n >= 7F
16 and MP0 = 1;
n,MP <-- normalized n,MP;
PI6 <-- 1, EA <-- 0, MA <-- 0, exit, if n < 80
16;
EA <-- n;
MA <-- MP0-23;
(CS) <-- 0010 if (RA,RA+1) = 0;
(CS) <-- 0001 if (RA,RA+1) < 0;
(CS) <-- 0100 if (RA,RA+1) >= 0;
Registers Affected. RA, RA+1, CS, PI