| MIL-STD-1750A: Military Standard Sixteen-Bit Computer Instruction Set Architecture | ||
|---|---|---|
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Addr
Mode Mnemonic Format/Opcode
8 4 4
----------------------
R MSR RA,RB | C1 | RA | RB |
----------------------
8 4 4
----------------------
ISP MISP RA,N | C2 | RA | N-1 | 1 <= N <= 16
----------------------
8 4 4
----------------------
ISN MISN RA,N | C3 | RA | N-1 | 1 <= N <= 16
----------------------
8 4 4 16
D MS RA,ADDR --------------------------------------
DX MS RA,ADDR,RX | C0 | RA | RX | | ADDR |
--------------------------------------
8 4 4 16
--------------------------------------
IM MSIM RA,DATA | 4A | RA | 4 | | DATA |
--------------------------------------
Description. The Derived Operand, DO, is multiplied by the contents of register RA. The LSH of the result, a 16-bit, 2's complement integer, is stored in register RA. The Condition Status, CS, is set based on the result in register RA. A fixed point overflow occurs if (1) both operands are of the same sign and the MSH of the product is not zero, or the sign bit of the LSH is not zero, or (2) if the operands are of opposite sign and the MSH of the product is not FFFF16, or the sign bit of the LSH is not one. A fixed point overflow does not occur if either of the operands is zero.
Register Transfer Description.
(RQ,RQ+1)1 <-- (RA) x DO;
(RA)2 <-- (RQ+1);
PI4 <-- 1, if {(RA0)
1 = DO0 and {(RQ) /= 0 or (RQ+1
0) = 1}} or
{(RA0)1 /= DO
0 and {(RQ) /= FFFF16 or (RQ+1
0) = 0} and
{(RA)1 /= 0 and DO /= 0}};
(CS) <-- 0010 if (RA) = 0;
(CS) <-- 0001 if (RA) < 0;
(CS) <-- 0100 if (RA) >= 0;
Registers Affected. RA, CS, PI