| MIL-STD-1750A: Military Standard Sixteen-Bit Computer Instruction Set Architecture | ||
|---|---|---|
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Addr
Mode Mnemonic Format/Opcode
8 4 4
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R FNEG RA,RB | BC | RA | RB |
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Description. The 24-bit mantissa of the Derived Operand, DO, i.e., the floating point number in registers RB and RB+1, is 2's complemented. The exponent remains unchanged. The result, the negative of the original number, is stored in RA and RA+1. The 2's complement of a floating point zero is a floating point zero. Exceptions to this are all powers of two: -1.0 x 2n and 0.5 x 2n-1, i.e., when the mantissa either 8000 0016 or 4000 0016. The negation of 0.5 x 2n is -1.0 x 2n-1, i.e., the mantissa is shifted left one position and the exponent decremented by one. Conversely, the negation of -1.0 x 2n is 0.5 x 2n-1; i.e., the mantissa is shifted right one position and the exponent is incremented by one. A floating point overflow occurs for the negation of the smallest negative number, -1.0 x 2127. A floating point underflow occurs for the negation of the smallest positive number, 0.5 x 2-128, and causes the result to be zero. The condition status, CS, is set based on the result in registers RA and RA+1.
Note: RA may equal RB.
Register Transfer Description.
PI3 <-- 1, EA <-- 7F
16, MO <-- 7FFF FF16, exit, if DO = 8000 007F
16;
PI3 <-- 1, EA <-- 0, MA <-- 0, exit, if DO = 4000 0080
16;
EA <-- EO+1, MA <-- 4000 00
16, if MO = 8000 0016;
EA <-- EO-1, MA <-- 8000 00
16, if MO = 4000 0016;
EA <-- EO, MA <-- -MO, if MO /= 8000 00
16 or 4000 0016;
(CS) <-- 0010 if (RA,RA+1) = 0;
(CS) <-- 0001 if (RA,RA+1) < 0;
(CS) <-- 0100 if (RA,RA+1) >= 0;
Registers Affected. RA, RA+1, CS, PI