| MIL-STD-1750A: Military Standard Sixteen-Bit Computer Instruction Set Architecture | ||
|---|---|---|
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Addr
Mode Mnemonic Format/Opcode
8 4 4 16
D EFST RA,ADDR --------------------------------------
DX EFST RA,ADDR,RX | 9A | RA | RX | | ADDR |
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Description. The contents of registers RA, RA+1, RA+2 are stored at the Derived Address, DA, DA+1, and DA+2.
Register Transfer Description.
[DA, DA+1, DA+2] <-- (RA, RA+1, RA+2);
Registers Affected. None