| MIL-STD-1750A: Military Standard Sixteen-Bit Computer Instruction Set Architecture | ||
|---|---|---|
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Addr
Mode Mnemonic Format/Opcode
8 4 4
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R RVBR RA,RB | 5C | RA | RB |
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Description. Bit number N (0 <= N <= 15) of register RB is set to zero where the least significant four bits of the contents of register RA is N. Bits (RA)0-11 have no effect on the operation. If RA = RB, then the count is determined first and then the appropriate bit is changed.
Register Transfer Description.
(RB)N <-- 012-15 where N = (RA) ;
Registers Affected. RB