| Getting Started with ERC32 Ada: Ada 95 Compilation System for Spacecraft Microprocessors | ||
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Table B-1 describes the mapping of a set of synthetic (or "pseudo") instructions to actual ERC32 instructions. These synthetic instructions are provided by the ERC32 assembler for the convenience of assembly language programmers.
Note that synthetic instructions should not be confused with pseudo-ops,which typically provide information to the assembler but do not generate instructions. Synthetic instructions always generate instructions; they provide a more mnemonic syntax for standard ERC32 instructions.
The data in this table is based on Appendix A of The SPARC Architecture Manual, published by SPARC International, Inc.
Table B-1. Mapping of Synthetic Instructions to ERC32 Instructions
| Synthetic Instruction | ERC32 Instruction(s) | Comment |
|---|---|---|
| cmp regrs1,reg_or_imm | subcc regrs1,reg_or_imm,%g0 | compare |
| jmp address | jmpl address,%g0 | |
| call address | jmpl address,%o7 | |
| tst regrs2 | orcc %g0,regrs2,%g0 | test |
| ret | jmpl %i7+8,%g0 | return from subroutine |
| retl | jmpl %o7+8,%g0 | return from leaf subroutine |
| restore | restore %g0,%g0,%g0 | trivial restore |
| save | save %g0,%g0,%g0 | trivial save (Warning: trivial save should only be used in kernel code! ) |
| set value,regrd | sethi %hi(value,regrd | (when ((value & 0x1fff) == 0)) |
| or | ||
| or %g0,value,regrd | (when -4096 <= value <= 4095) | |
| or | ||
| sethi %hi(value,regrd; | (otherwise) | |
| or regrd,%lo(value),regrd | ||
| not regrs1,regrd | xnor regrs1,%g0,regrd | one's complement |
| not regrd | xnor regrd,%g0,regrd | one's complement |
| neg regrs2,regrd | sub %g0,regrs2, regrd | two's complement |
| neg regrd | sub %g0,regrd,regrd | two's complement |
| inc regrd | add regrd,1,regrd | increment by 1 |
| inc const13,regrd | add regrd,const13 ,regrd | increment by const13 |
| inccc regrd | addcc regrd,1,regrd | increment by 1 and set icc |
| inccc const13,regrd | addcc regrd,const13,regrd | increment by const13 and set icc |
| dec regrd | sub reg,1,regrd | decrement by 1 |
| dec const13,regrd | sub reg,const13,regrd | decrement by const13 |
| deccc regrd | subcc reg,1,regrd | decrement by 1 and set icc |
| deccc const13,regrd | subcc regrd,const13,regrd | decrement by const13 and set icc |
| btst reg_or_imm,regrs1 | andcc regrs1,reg_or_imm,%g0 | bit test |
| bset reg_or_imm,regrd | or regrd,reg_or_imm,regrd | bit set |
| bclr reg_or_imm,regrd | andn regrd,reg_or_imm,regrd | bit clear |
| btog reg_or_imm,regrd | xor regrd,reg_or_imm,regrd | bit toggle |
| clr regrd | or %g0,%g0,regrd | clear(zero) register |
| clrb [address] | stb %g0,[address] | clear byte |
| clrh [address] | sth %g0,[address] | clear halfword |
| clr [address] | st %g0,[address] | clear word |
| mov reg_or_imm,regrd | rd %g0,reg_or_imm,regrd | |
| mov %y,regrd | rd %y,regrd | |
| mov %asrn,regrd | rd %asrn,regrd | |
| mov %psr,regrd | rd %psr,regrd | |
| mov %wim,regrd | rd %wim,regrd | |
| mov %tbr,regrd | rd %tbr,regrd | |
| mov reg_or_imm,%y | wr %g0,reg_or_imm,%y | |
| mov reg_or_imm,%asrn | wr %g0,reg_or_imm,%asrn | |
| mov reg_or_imm,%psr | wr %g0,reg_or_imm,%psr | |
| mov reg_or_imm,%wim | wr %g0,reg_or_imm,%wim | |
| mov reg_or_imm,%tbr | wr %g0,reg_or_imm,%tbr |