5.80. Extended Precision Floating Point Divide


Addr
Mode  Mnemonic          Format/Opcode
                           8      4      4
                        ----------------------
R     EFDR   RA,RB      |  DB  |  RA  |  RB  |
                        ----------------------
                           8      4      4           16
D     EFD    RA,ADDR    --------------------------------------
DX    EFD    RA,ADDR,RX |  DA  |  RA  |  RX  |  |    ADDR    |
                        --------------------------------------

Description. The contents of registers RA, RA+1, and RA+2 are extended precision floating point divided by the extended precision floating point Derived Operand, DO. The result is stored in register RA, RA+1, and RA+2. A floating point overflow occurs if the exponent result exceeds 7F16 at any point in the calculation process. Underflow occurs if the exponent result is less than 8016 at any point in the process. If underflow occurs, then the quotient is forced to zero. A divide by zero yields a floating point overflow.

Register Transfer Description.

n = EA - E0;
n <-- 0, if MA = 0;
PI3 <-- 1, EA <-- 7F 16, MA <-- 7FFF FF FFFF 16, exit, if MA0 = MO 0 and {n >= 7F16or DO = 0};
PI3 <-- 1, EA <-- 7F 16, MA <-- 8000 00 0000 16, exit, if MA0 /= MO 0 and {n >= 7F16or DO = 0};
PI6 <-- 1, EA <-- 0, MA <-- 0, exit, if n < 80 16;
MQ <-- MA / MO;
MQ <-- MQ Shift Right Arithmetic 1 position, n <-- n + 1, if MQ >== 1.0;
                                                         
PI3 <-- 1, EA <-- 7F 16, MA <-- 7FFF FF FFFF 16, exit, if n >= 7F16 and MQ 0 = 0;
PI3 <-- 1, EA <-- 7F 16, MA <-- 8000 00 0000 16, exit, if n >= 7F16 and MQ 0 = 1;
EA <-- n;
MA <-- MQ0-39;
(CS) <-- 0010  if (RA,RA+1,RA+2) = 0;
(CS) <-- 0001  if (RA,RA+1,RA+2) < 0;
(CS) <-- 0100  if (RA,RA+1,RA+2) > 0;



Registers Affected. RA, RA+1, RA+2, CS, PI