5.38. Single Precision Load


Addr
Mode  Mnemonic          Format/Opcode
                           8      4      4
                        ----------------------
R     LR    RA,RB       |  81  |  RA  |  RB  |
                        ----------------------
                           4     2     2        8       12<=BR<=15
                        ------------------------------  
B     LB    BR,DSPL     |  0  |  0  |  BR'  |  DSPL  |  BR'=BR-12
                        ------------------------------  RA=R2
                           4     2    2      4    4     12<=BR<=15
                        ------------------------------   
BX    LBX   BR,RX       |  4  |  0 |  BR' |  0 |  RX |  BR'=BR-12
                        ------------------------------  RA=R2
                           8      4       4
                        -----------------------
ISP   LISP  RA,N        |  82  |  RA  |  N-1  |         1<=N<=16
                        -----------------------   
                           8      4       4
                        -----------------------
ISN   LISN  RA,N        |  83  |  RA  |  N-1  |         1<=N<=16
                        -----------------------  
                           8      4      4            16
D     L     RA,ADDR     --------------------------------------
DX    L     RA,ADDR,RX  |  80  |  RA  |  RX  |  |    ADDR    |
                        --------------------------------------
                           8      4      4            16
IM    LIM   RA,DATA     --------------------------------------
IMX   LIM   RA,DATA,RX  |  85  |  RA  |  RX  |  |    DATA    |
                        --------------------------------------
                           8      4      4            16
I     LI    RA,ADDR     --------------------------------------
IX    LI    RA,ADDR,RX  |  84  |  RA  |  RX  |  |    ADDR    |
                        --------------------------------------

Description. The single precision Derived Operand, DO, is loaded into the register RA. The Condition Status, CS, is set based on the result in register RA.

Register Transfer Description.

(RA) <-- DO;
(CS) <-- 0010  if (RA) = 0;
(CS) <-- 0001  if (RA) < 0;
(CS) <-- 0100  if (RA) > 0;



Registers Affected. RA, CS