5.35. Load Status


Addr
Mode  Mnemonic          Format/Opcode
                           8       4      4            16
D     LST   ADDR        --------------------------------------
DX    LST   ADDR,RX     |  7D  | 0000 |  RX  |  |    ADDR    |
                        --------------------------------------
                           8       4      4            16
I     LSTI  ADDR        --------------------------------------
IX    LSTI  ADDR,RX     |  7C  | 0000 |  RX  |  |    ADDR    |
                        --------------------------------------

Description. The contents of the Derived Address, DA, and DA+1, and DA+2 are loaded into the Interrupt Mask register, Status Word register and Instruction Counter, respectively. This is a privileged instruction.

Note: This instruction is an unconditional jump and is typically used to exit from an interrupt routine. DA, DA+1, and DA+2, in this typical case, contain the Interrupt Mask, Status Word, and Instruction Counter values for the interrupted program and the execution of LST causes the program to return to its status prior to being interrupted.

Register Transfer Description.

(MK, SW, IC) <-- [DA, DA+1, DA+2];



Registers Affected. MK, SW, IC