5.17. Double Shift Left Cyclic


Addr
Mode  Mnemonic          Format/Opcode
                           8       4      4
                        -----------------------
R     DSLC   RB,N       |  68  |  N-1  |  RB  |     1 <= N <= 16
                        -----------------------

Description. The concatenated contents of the Derived Address, DA, and DA+1 (i.e., the concatenated contents of RB and RB+1), are shifted left cyclically N positions. The shifted results are stored in RB and RB+1. The double left shift cyclic operation is as follows: bits shifted out of the sign bit position of RB enter the least significant bit position of RB+1, bits shifted out of the sign bit position of RB+1 enter the least significant bit position of RB, and, consequently, no bits are lost. The condition status, CS, is set based on the result in RB and RB+1.

Note: N-1 = 0 represents a shift of one position.

Note: N-1 = 15 represents a shift of sixteen positions.


                       RB, RB+1 Before Shift
 0            RB           15       0          RB+1           15
------------------------------     ------------------------------
| s abc | defg | hijk | lmnp |     | s qrs | tuvw | xyzz | zzzz |
|  1    |      |      |      |     |  2    |      |      |      |
------------------------------     ------------------------------
                       RB, RB+1 After Shift (N=4)
 0            RB           15       0          RB+1           15
------------------------------     ------------------------------
| defg | hijk | lmnp | s qrs |     | tuvw | xyzz | zzzz | s abc |
|      |      |      |  2    |     |      |      |      |  1    |
------------------------------     ------------------------------

Register Transfer Description.

(RB,RB+1) <-- (RB,RB+1) Shifted left cyclically by N positions;
(CS) <-- 0010  if (RB,RB+1) = 0;
(CS) <-- 0001  if (RB,RB+1) < 0;
(CS) <-- 0100  if (RB,RB+1) > 0;



Registers Affected. RB, RB+1, CS