5.10. Shift Left Logical


Addr
Mode  Mnemonic          Format/Opcode
                           8       4      4
                        -----------------------
R     SLL  RB,N         |  60  |  N-1  |  RB  |   1 <= N <= 16
                        -----------------------

Description. The contents of the Derived Address, DA (i.e., the contents of register RB) are shifted left logically N positions. The shifted result is stored in RB. The logical shift left operation is as follows: zeros enter the least significant bit position (bit 15) and bits shifted out of the sign bit position (bit 0) are lost. The condition status, CS, is set based on the result in register RB.

Note: N-1 = 0 represents a shift of one position.

Note: N-1 = 15 represents a shift of sixteen positions.


                               0                        15
                              -----------------------------
RB Before Shift               | sabc | defg | hijk | lmnp |
                              -----------------------------
                              -----------------------------
RB After Shift (N=4)          | defg | hijk | lmnp | 0000 |
                              -----------------------------

Register Transfer Description.

(RB) <-- (RB) Shifted left logically by N positions;
(CS) <-- 0010  if (RB) = 0;
(CS) <-- 0001  if (RB) < 0;
(CS) <-- 0100  if (RB) > 0;



Registers Affected. RB,CS