5.4. Reset Bit


Addr
Mode  Mnemonic          Format/Opcode
                           8      4     4
                        ---------------------
R     RBR   N,RB        |  54  |  N  |  RB  |
                        ---------------------
                           8      4     4            16
D     RB    N,ADDR      --------------------------------------
DX    RB    N,ADDR,RX   |  53  |  N  |  RX  |  |    ADDR     |
                        --------------------------------------
                           8      4     4            16
I     RBI   N,ADDR      --------------------------------------
IX    RBI   N,ADDR,RX   |  55  |  N  |  RX  |  |    ADDR     |
                        --------------------------------------

Description. Bit number N of the Derived Operand, DO, is set to zero. The MSB is designated bit number zero and the LSB is designated bit number fifteen.

Register Transfer Description.

DON <-- 0;



Registers Affected. RB