| MIL-STD-1750A: Military Standard Sixteen-Bit Computer Instruction Set Architecture | ||
|---|---|---|
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Addr
Mode Mnemonic Format/Opcode
8 4 4
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R EFLT RA,RB | EB | RA | RB |
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Description. The double precision integer Derived Operand, DO (i.e., the contents of registers RB and RB+1), is converted to Extended Precision floating point format and stored in register RA, RA+1, and RA+2. The condition status, CS, is set based on the result in RA, RA+1, and RA+2. The operation process is as follows: The exponent is initially considered to be 1F16. The integer value in RB, RB+1 is normalized, i.e., the number is left shifted and the exponent decremented for each shift until the sign bit and the next MSB are unequal, and the exponent and mantissa stored in the proper field of RA, RA+1, and RA+2.
Note: RA may equal RB.
Register Transfer Description.
EA <-- 0, MA <-- 0, exit, if (RB,RB+1) = 0;
EA <-- 1F16, MA <-- (RB,RB+1);
EA, MA <-- normalized EA, MA;
(CS) <-- 0010 if (RA,RA+1,RA+2) = 0;
(CS) <-- 0001 if (RA,RA+1,RA+2) < 0;
(CS) <-- 0100 if (RA,RA+1,RA+2) >= 0;
Registers Affected. RA, RA+1, RA+2, CS