| MIL-STD-1750A: Military Standard Sixteen-Bit Computer Instruction Set Architecture | ||
|---|---|---|
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Addr
Mode Mnemonic Format/Opcode
8 4 4
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R FIX RA,RB | E8 | RA | RB |
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Description. The integer portion of the floating point Derived Operand, DO (i.e., the contents of registers RB and RB+1), is stored into register RA. If the actual value of the DO floating point exponent is greater than 0F16, then RA remains unchanged and a fixed point overflow occurs. The condition status, CS, is set based on the result in RA.
Note: The algorithm truncates toward zero.
Register Transfer Description.
PI4 <-- 1, exit, if EO >= 0F
16;
(RA) <-- Integer portion of DO;
(CS) <-- 0010 if (RA) = 0;
(CS) <-- 0001 if (RA) < 0;
(CS) <-- 0100 if (RA) >= 0;
Registers Affected. RA, CS, PI