| MIL-STD-1750A: Military Standard Sixteen-Bit Computer Instruction Set Architecture | ||
|---|---|---|
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Addr
Mode Mnemonic Format/Opcode
8 4 4
----------------------
R DDR RA,RB | D7 | RA | RB |
----------------------
8 4 4 16
D DD RA,ADDR --------------------------------------
DX DD RA,ADDR,RX | D6 | RA | RX | | ADDR |
--------------------------------------
Description. The contents of registers RA and RA+1, a double precision 2's complement number, are divided by the Derived Operand, DO, a double precision 2's complement number. RA contains the MSH of the 32-bit dividend. The quotient part of the integer result is stored in registers RA and RA+1 (with the MSH in RA) and the remainder is lost. The Condition Status, CS, is set based on the results in registers RA and RA+1. A fixed point overflow occurs if the divisor, DO, is zero, or if the dividend is 8000 000016 and the divisor is FFFF FFFF16.
Register Transfer Description.
(RA,RA+1) <-- (RA,RA+1) / DO;
PI4 <-- 1, if DO = 0 or {RA, RA+1 = 8000 0000
16 and DO = FFFF FFFF16};
(CS) <-- 0010 if (RA,RA+1) = 0;
(CS) <-- 0001 if (RA,RA+1) < 0;
(CS) <-- 0100 if (RA,RA+1) >= 0;
Registers Affected. RA, RA+1, CS, PI