| MIL-STD-1750A: Military Standard Sixteen-Bit Computer Instruction Set Architecture | ||
|---|---|---|
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Addr
Mode Mnemonic Format/Opcode
8 4 4 16
D DECM N,ADDR ---------------------------------------
DX DECM N,ADDR,RX | B3 | N-1 | RX | | ADDR |
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Description. The contents of the memory location specified by the Derived Address, DA, are decremented by N, where N is an integer, 1 <= N <= 16. This is equivalent of a "subtract-from-memory instruction". The condition status, CS, is set based on the results of the subtraction and carry. A fixed point overflow occurs if the operand in memory is negative and the result is positive. The memory location specified is updated to contain the result of the subtraction process even if a fixed point overflow occurs.
Register Transfer Description.
[DA]2 <-- [DA]1 - N, where 1 <= N <= 16;
PI4 <-- 1, if [DA0]
1 < 0 < [DA0]
2;
(CS) <-- 0010 if carry = 0 and [DA] = 0;
(CS) <-- 0001 if carry = 0 and [DA] < 0;
(CS) <-- 0100 if carry = 0 and [DA] >= 0;
(CS) <-- 1010 if carry = 1 and [DA] = 0;
(CS) <-- 1001 if carry = 1 and [DA] < 0;
(CS) <-- 1100 if carry = 1 and [DA] >= 0;
Registers Affected. CS, PI