| MIL-STD-1750A: Military Standard Sixteen-Bit Computer Instruction Set Architecture | ||
|---|---|---|
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Addr
Mode Mnemonic Format/Opcode
8 4 4
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R FABS RA,RB | AC | RA | RB |
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Description. If the sign bit of the mantissa of the Derived Operand, DO (i.e., the contents of registers RB and RB+1), is a one, its floating point negative is stored in registers RA and RA+1. The negative of DO is computed by taking the 2's complement of the mantissa and leaving the exponent unchanged. Exceptions to this are negative powers of two: -1.0 x 20, -1.0 x 21, ... . The absolute value of these are: 0.5 x 21, 0.5 x 22, ..., in other words, the DO mantissa is shifted logically right one position and the exponent incremented. A floating point overflow shall occur if DO is the smallest negative number, -1.0 x 2127. If the sign bit of DO is a zero, it is stored unchanged into RA and RA+1. The condition status, CS, is set based on the result in register RA and RA+1.
Note: RA may equal RB.
Note: DO is assumed to be a normalized number or floating point zero.
Register Transfer Description.
EA <-- EA+1, MA <-- 4000 00
16, if MO = 8000 0016;
PI3 <-- 1, EA <-- 7F
16, MA <-- 7FFF FF16, exit, if EA >= 7F
16;
EA <-- EO, MA <-- -MO, if MO < 0, if MO /= 8000 00
16;
EA <-- EO, MA <-- MO, if MO >= 0;
(CS) <-- 0010 if (RA,RA+1) = 0;
(CS) <-- 0001 if (RA,RA+1) < 0;
(CS) <-- 0100 if (RA,RA+1) >= 0;
Registers Affected. RA, RA+1, CS, PI