| MIL-STD-1750A: Military Standard Sixteen-Bit Computer Instruction Set Architecture | ||
|---|---|---|
| Prev | Chapter 5. Detailed Requirements | Next |
Addr
Mode Mnemonic Format/Opcode
8 4 4
----------------------
R DAR RA,RB | A7 | RA | RB |
----------------------
8 4 4 16
D DA RA,ADDR --------------------------------------
DX DA RA,ADDR,RX | A6 | RA | RX | | ADDR |
--------------------------------------
Description. The double precision Derived Operand (DO) is added to the contents of registers RA and RA+1. The result (a 2's complement 32-bit sum) is stored in registers RA and RA+1. The MSH is in RA. The condition status (CS) is set based on the double precision results in RA and RA+1, and carry. A fixed point overflow occurs if both operands are of the same sign and the sum is of opposite sign.
Register Transfer Description.
(RA,RA+1)2 <-- (RA,RA+1)1 + DO;
PI4 <-- 1 if (RA
0)1 = DO0 and (RA
0)1 /= (RA0)
2
(CS) <-- 0010 if carry = 0 and (RA,RA+1) = 0;
(CS) <-- 0001 if carry = 0 and (RA,RA+1) < 0;
(CS) <-- 0100 if carry = 0 and (RA,RA+1) >= 0;
(CS) <-- 1010 if carry = 1 and (RA,RA+1) = 0;
(CS) <-- 1001 if carry = 1 and (RA,RA+1) < 0;
(CS) <-- 1100 if carry = 1 and (RA,RA+1) >= 0;
Registers Affected. RA, RA+1, CS, PI