| MIL-STD-1750A: Military Standard Sixteen-Bit Computer Instruction Set Architecture | ||
|---|---|---|
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Addr
Mode Mnemonic Format/Opcode
8 4 4
----------------------
R AR RA,RB | A1 | RA | RB |
----------------------
4 2 2 8 12<=BR<=15
----------------------
B AB BR,DSPL | 1 | 0 | BR' | DSPL | BR'=BR-12
---------------------- RA=R2
4 2 2 4 4 12<=BR<=15
------------------------
BX ABX BR,RX | 4 | 0 | BR' | 4 | RX | BR'=BR-12
------------------------ RA=R2
8 4 4
-----------------------
ISP AISP RA,N | A2 | RA | N-1 | 1<N<16
-----------------------
8 4 4 16
D A RA,ADDR --------------------------------------
DX A RA,ADDR,RX | A0 | RA | RX | | ADDR |
--------------------------------------
8 4 4 16
--------------------------------------
IM AIM RA,DATA | 4A | RA | 1 | | DATA |
--------------------------------------
Description. The Derived Operand (DO) is added to the contents of the RA register. The result (a 2's complement sum) is stored in register RA. The condition status (CS) is set based on the result in register RA and carry. A fixed point overflow occurs if both operands are of the same sign and the sum is of opposite sign.
Register Transfer Description.
(RA)2 <-- (RA)1 + DO;
PI4 <-- 1, if (RA0)
1 = DO0 and (RA0)
1 /= (RA0)2
(CS) <-- 0010 if carry = 0 and (RA) = 0;
(CS) <-- 0001 if carry = 0 and (RA) < 0;
(CS) <-- 0100 if carry = 0 and (RA) >= 0;
(CS) <-- 1010 if carry = 1 and (RA) = 0;
(CS) <-- 1001 if carry = 1 and (RA) < 0;
(CS) <-- 1100 if carry = 1 and (RA) >= 0;
Registers Affected. RA, CS, PI