| MIL-STD-1750A: Military Standard Sixteen-Bit Computer Instruction Set Architecture | ||
|---|---|---|
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Addr
Mode Mnemonic Format/Opcode
8 4 4
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R SLC RB,N | 63 | N-1 | RB | 1 <= N <= 16
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Description. The contents of the Derived Address, DA (i.e., the contents of register RB), are shifted left cyclically N positions. The shifted result is stored in RB. The cyclic left shift operation is as follows: bits shifted out of the sign bit position (bit 0) enter the least significant bit position (bit 15) and, consequently, no bits are lost. The condition status, CS, is set based on the result in RB.
Note: N-1 = 0 represents a shift of one position.
Note: N-1 = 15 represents a shift of sixteen positions.
0 15
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RB Before Shift | sabc | defg | hijk | lmnp |
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RB After Shift (N=4) | defg | hijk | lmnp | sabc |
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Register Transfer Description.
(RB) <-- (RB) Shifted left cyclically by N positions;
(CS) <-- 0010 if (RB) = 0;
(CS) <-- 0001 if (RB) < 0;
(CS) <-- 0100 if (RB) >= 0;
Registers Affected. RB,CS