| MIL-STD-1750A: Military Standard Sixteen-Bit Computer Instruction Set Architecture | ||
|---|---|---|
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Addr
Mode Mnemonic Format/Opcode
8 4 4
---------------------
R TBR N,RB | 57 | N | RB |
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8 4 4 16
D TB N,ADDR --------------------------------------
DX TB N,ADDR,RX | 56 | N | RX | | ADDR |
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8 4 4 16
I TBI N,ADDR --------------------------------------
IX TBI N,ADDR,RX | 58 | N | RX | | ADDR |
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Description. Bit number N (0 <= N <= 15) of the Derived Operand, DO, is tested. Then the Condition Status, CS, is set to indicate non-zero if bit number N of the DO contains a one. Otherwise CS is set to indicate zero. The MSB of the DO is designated bit number zero and the LSB of the DO is designated bit number fifteen.
Register Transfer Description.
(CS) <-- 0010 if DON = 0 and 0 <= N <= 15;
(CS) <-- 0001 if DON = 1 and N = 0;
(CS) <-- 0100 if DON = 1 and 1 <= N <= 15;
Registers Affected. CS