| Getting Started with GCC-ERC32: C/C++ Compilation System for Mission Critical Spacecraft Applications | ||
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Using memory that is 40 bits wide, the ERC32's EDAC can correct single-bit errors in any 32-bit word, and can detect any double-bit error. The version 1.7 simulator contains a simulation of the EDAC and by default, this is switched off. In this state, the additional 8 bits of information are generated on each write to an EDAC-protected area of memory, but are not tested on memory reads.
The ERC32 offers EDAC protection for RAM, for ERAM and for the boot PROM, provided the PROM is the 40-bit wide kind. The 8-bit PROM has no EDAC protection, and no parity protection either. When EDAC simulation is switched on, then depending on further options set in the system registers, the EDAC may be used to correct and detect errors in memory. This raises several issues, some of which are very important from the point of view of running the odd test program.
If you are simulating the 40-bit boot PROM, then the PROM must contain the extra 8 bits for each 32 bits of data. Normally you will use a tool to generate these bits and program them into the PROM or PROMs along with the rest of the data. To make life easier, the simulator's load function generates these extra bits for you. This means you can load a normal 32-bit wide program.
Similarly if the simulator loads your program directly into RAM or ERAM, which is the case for prgorams built using the default options, it generates the checkbits. Of course, on the real target, this would happen without any special intervention because the loader would simply write your program to RAM with the EDAC generating the checkbits.
For a data item that is 32 bits in size, the first memory write will write both the data and the extra check bits required by the EDAC. For byte size and half-word size items, the ERC32 will do a read-modify-write memory cycle with EDAC checking on the read and checkbit generation on the write. This means that byte size and half-word size items cannot be initialized individually; the initial memory write must be a whole word write otherwise the EDAC will report a failure when it reads the uninitialized memory word.
One solution to this is to initialize the whole of RAM and ERAM before the application program runs. This may take some time, possibly up to 20 seconds for a large memory.
In version 1.7, the cold-start emulation includes code that writes zero to each location in RAM. The size of memory is known to art0 and this will need to be customized if your memory is not the same size. Also, if you wish to initialize ERAM, you will need to add code to art0.
For application programs that do not include the code start code, and this will be the majority of test programs, benchmarks and so on, we have the same EDAC problem. We therefore recommend running such programs with the EDAC switched off, and have set the EDAC option to off by default.
If you wish to test your EDAC code, then one way to test at least part of it is to use the EDAC test feature offered by the ERC32 (and by the simulator). This allows you to specify the seven check bits on memory writes, and thereby introduce single-bit errors. You cannot introduce single-bit errors into the 32-bits of data because the EDAC write circuitary will always generate a correct parity bit and thwart any attemp to write data with bad parity (which indicates a single bit error).
You can of course read the contents of memory location and write it back with one or more of the bits changed. If you do this keeping the checkbits for the original contents then you will always get an uncorrctable error on the next read of that location.
Version 1.7 also includes a generator for random single-bit errors that can be written to a random memory location at a given frequency, say one error per second, or maybe faster for times when you are keen to see you error recovery code working hard.
In the following example we run a program that requires the EDAC. We introduce random SEU errors into RAM at a rate of 100000 per MB per day, which for a 8MB RAM is aproximately 9 per second.
Example 2-16. Running the simulator with the EDAC
$ erc-coff-run my_program -a "-edac -mer 100000 -trace-edac" Setting memory error rate to 100000 per MB per day Tracing EDAC errors 17280000: SEU before: addr 0035c5a0 bit 15, p 0, cb 00, data 00000000 17280000: ... after: p 0, cb 00, data 01000000 34560000: SEU before: addr 00321e4c bit 31, p 0, cb 00, data 00000000 34560000: ... after: p 0, cb 00, data 00000100 ...