The 1750 does not have the important load register instruction for extended precision floating point. The reason is we can copy a three-word extended floating point value from one triple register to another using a single load register and a double load register. However, if the source triple and destination triples overlap, then it is important to get the single and double load in the correct order otherwise the source will be overwritten before it is completely copied.
The opcode “eflr” is translated by the assembler into either a single load followed by a double load, or a double load followed by a single load, depending on which registers are used, and guarantees correct operation.
Note that the condition codes will not be correctly set by eflr. To set the condition codes you should do an extended compare with zero. Of course to check whether a number is negative or not, no matter whether it is a 16 bit, 32 bit or 48 bit, fixed or floating, you only have to test the sign bit of the first word.
There are two macro-like instructions, LSJS and LURS, for supporting subprogram call and return across address states. Normally these will be translated by the assembler into SJS and URS instructions, but if the assembler is run with the expanded memory option -Ammu then LSJS is expended into an sequence of instructions that makes a call to a subprogram that may be in a different address state. The LURS instruction is converted into a LST instruction, using the register given in the LURS instruction (usually R15), and an offset of zero.
The instruction LLIM is used to load a long (24-bit) word address into a pair of registers. The address can then be used in the 1750B long load and store instructions, such as LSL and LSS.
Certain pseudo opcodes are permitted for branch instructions. They expand to the shortest branch instruction that reach the target. Generally these mnemonics are made by substituting “j” for “b” at the start of a 1750 mnemonic.
The following table summarizes the pseudo-operations.
Table 30-1. M1750 Pseudo Operations
| Pseudo Op | 16-bit instruction | 32-bit instruction |
|---|---|---|
j L1 |
br L1 |
jc uc,L1 |
jeq L1 |
beq L1 |
jc eq,L1 |
jne L1 |
bne L1 |
jc ne,L1 |
jgt L1 |
bgt L1 |
jc gt,L1 |
jlt L1 |
blt L1 |
jc lt,L1 |
jge L1 |
bge L1 |
jc ge,L1 |
jle L1 |
ble L1 |
jc le,L1 |
All the MIL-STD-1750A and 1750B XIO commands are supported.
BIT, CC, CI, CLC, CLIR, CO, DMAD, DMAE, DSBL, DSUR, ENBL, ESUR, GO, ICW, ITA, ITAR, ITB, ITBR, ITGI, LMP, LOS, LXMP, MPEN, OD, OTA, OTAR, OTB, OTBR, OTGR, PI, PO, RCFR, RCS, RCW, RDI, RDOR, RDOW, RFMK, RFR, RIC1, RIC2, RIPR, RLP, RMFA, RMFP, RMFS, RMK, RMP, RNS, ROPR, ROS, RPBS, RPI, RPIR, RPS, RSW, RXMP, SFMK, SFR, SMK, SPI, TAH, TAS, TBH, TBS, TPIO, WIPR, WOPR, WPBS, WSW
The line-comment character is “!”. If a “#” appears at the beginning of a line, it is treated as a comment unless it looks like “# line file”, in which case it is treated normally.